132 lines
2.3 KiB
C
132 lines
2.3 KiB
C
#include "i2c_master.h"
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#include <avr/io.h>
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uint8_t i2c_clock(uint8_t type);
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void i2c_init(void)
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{
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// Define SCL and SDA as Output
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DDRA |= (1 << 4) | (1 << 6);
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// Preload dataregister with "released level" data
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USIDR = 0xFF;
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// Use SCL and SDA pins
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// Select clock sources
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USICR = (1 << USIWM1) | (1 << USICS1) | (1 << USICLK);
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// Clear flags and reset counter
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USISR = (1 << USISIF) | (1 << USIOIF) | (1 << USIPF) | (1 << USIDC);
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}
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uint8_t i2c_start(uint8_t address)
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{
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// FOR REPEATED START
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// Release SCL
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PORTA |= (1 << 4);
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// Verify that SCL becomes high
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while (!( PINA & (1 << 4) ));
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// GENERATE START CONDITION
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// Force SDA LOW
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PORTA &= ~(1 << 6);
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// Pull SCL LOW
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PORTA &= ~(1 << 4);
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// Release SDA
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PORTA |= (1 << 6);
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return i2c_write(address);
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}
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uint8_t i2c_write(uint8_t data)
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{
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// Pull SCL LOW
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PORTA &= ~(1 << 4);
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// Setup data
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USIDR = data;
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// Send 8 bits on bus
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i2c_clock(8);
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// Enable SDA as input
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DDRA &= ~(1 << 6);
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// Receive 1 bit on bus & Check for NACK
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if (i2c_clock(1) & (1 << 0))
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{
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return 1;
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}
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return 0;
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}
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uint8_t i2c_read(uint8_t nack)
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{
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// Enable SDA as input.
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DDRA &= ~(1 << 6);
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// Read 8 bits
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uint8_t result = i2c_clock(8);
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if (nack)
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{
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// Load NACK
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USIDR = 0xFF;
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}
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else
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{
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// Load ACK
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USIDR = 0x00;
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}
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i2c_clock(1);
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return result;
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}
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void i2c_stop(void)
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{
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// Pull SDA low
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PORTA &= ~(1 << 6);
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// Release SCL
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PORTA |= (1 << 4);
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// Wait for SCL to go high
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while (!( PINA & (1 << 4) ));
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// Release SDA
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PORTA |= (1 << 6);
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}
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uint8_t i2c_clock(uint8_t count)
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{
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uint8_t reg_temp = (1 << USISIF) | (1 << USIOIF) | (1 << USIPF) | (1 << USIDC);
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// Counter counts number of edges
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// Overflow signals end of transmission
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reg_temp |= 16 - (count * 2);
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USISR = reg_temp;
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// Set clock source & toggle clock prepare
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reg_temp = (1 << USIWM1) | (1 << USICS1) | (1 << USICLK) | (1 << USITC);
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do
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{
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// Generate positve SCL edge.
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USICR = reg_temp;
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// Wait for SCL to go high
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while (!( PINA & (1 << 4)));
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// Generate negative SCL edge
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USICR = reg_temp;
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}
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// Wait for counter overflow (all edges are completed)
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while (!( USISR & (1 << USIOIF)));
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// Read data
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reg_temp = USIDR;
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// Load dataregister with "released level" data
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USIDR = 0xFF;
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// Enable SDA as output
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DDRA |= (1 << 6);
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return reg_temp;
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}
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